The present invention relates to a method for the production of semiconductor devices, and particularly, to a method capable of providing a direct interconnection between a diffused region and an interconnecting portion even though the region and portion have either n-type or p-type conductivity, so that the production process is simplified.
In the miniaturization of an integrated circuit (IC), it is generally important that the poly-crystal silicon (Si) used as a gate electrode is directly connected with diffusional regions by use of the poly-crystal silicon as an interconnecting portion. The general method, which is used in the above-mentioned technology, will be explained with reference to FIG. 1.
In the first step, as shown in FIG. 1(a), an oxidized layer 2 for isolation of the active regions is formed on a semiconductor such as silicon substrate 1 by means of a selective oxidation process such as the localized oxidization of silicon (LOCOS). A gate oxidized layer 3 made of silicon dioxide (SiO.sub.2) is formed by hydrochloric acid (HCl) oxidization or the like with a thickness of 10 nanometers (nm). After that, a polysilicon layer 4 is formed on the layer 3, with a thickness of 150 nm by means of a chemical vapor deposition (a CVD) method. A mask is formed in order to form a hole for connecting the polysilicon layer 4 with a diffusion layer region which will be described later by means of a photoetching process, and then a resist layer is coated on the layer 4 with a thickness of the stated length (as shown in FIG. 1(a)).
After that, as shown in FIG. 1(b), the hole for connecting the polysilicon layer 4 with the diffused region in the manner that the resist layer 5 is used as a mask, and a dry etching process such as a non-isotropic reactive ion etching is used. A part of the gate dioxide layer 3, which exists at the bottom of the hole for connection, is eliminated by using ammonium fluoride (NH.sub.4 F) or the like after the resist layer 5 is eliminated. A polysilicon layer 7 is formed by means of the CVD method, to a thickness of 50 nm, and then a diffused region 8 is formed in the manner whereby ions of 5.times.10.sup.15 /cm.sup.2 of phosphorus (P) is injected into the layer 7 using 50 KeV of energy (as shown in FIG. 1(b)).
A polysilicon layer 9 is then stacked on the layer 7, to a thickness of 100 nm by means of the CVD. The semiconductor substrate is treated with heat at 900 degrees for thirty minutes in an atmosphere of phosphorus oxychloride (POCl.sub.3), so that the stacked polysilicon layers 4, 7 and 9 have a lower electric resistance and so that the diffused region 8 is electrically activated.
Then, a resist layer 10 is coated on the polysilicon layer 9 to the thickness of the stated value, and a mask is formed by means of the photoetching process in order to form an interconnection which connects a gate electrode with the diffused region 8 (refer to FIG. 1(b)).
As shown in FIG. 1(c), the polysilicon layers 4, 7 and 9 are etched by non-isotropic reactive ion etching using the resist layer 10 as the mask, which is processed in the predetermined shape, so that a gate electrode 11a and an interconnection 11b are formed, and the interconnection 11b is formed in order to connect a diffused region which will be mentioned later.
After that, diffused regions 13a and 13b are formed using the gate electrode 11a as the mask by means of the ion infection of 5.times.10.sup.15 /cm.sup.2. Of arsenic (As) and 50 KeV of energy (See FIG. 1(c)).
As shown in FIG. 1(d), an inter-level dioxide layer 14 is formed in the manner whereby silicon-dioxide (SiO.sub.2) is stacked on the polysilicon layer 9 and the hole of the layers 4, 7 and 9, to a thickness of 500 nm and by means of the CVD method. A connection hole 15a is made to connect with the diffused region 13a while a connection hole 15b is made to connect with the interconnection 11b. After that, a metal interconnection 16 is formed in the manner whereby aluminum (Al) is piled up on the surface with a thickness of 500 nm by a spattering method and using the combination with the photoetching process and non-isotropic reactive ion etching, so that the semiconductor device is completed.
However, since the diffused regions 13a and 13b have to be of the same conductive type as the interconnection 11a and 11b in order to directly connect with the regions 13a and 13b respectively, when the conventional method is used, the diffused region 13 is capable of directly connecting with the interconnection 11 only when both conductive types of the interconnection 11 and region 13 are the same. For instance, when the interconnection 11 is of the n-type, the interconnection 11 only connects with the diffused region 13 having the n conductive type.
Furthermore, it is a problem that a portion 12 generates electrical leaks easily so as to cause the characteristics of the semiconductor device to deteriorate, because the portion 12 of the silicon substrate 1 is etched with the etching of the polysilicon layers 4, 7 and 9, as shown in FIG. 1(c).
In addition, it is necessary not only that the photoetching process be performed twice in order to make the connection hole for directly connecting the interconnection 11b with the diffused region 13b, but also that the polysilicon layers are stacked three times. Furthermore, it is also necessary to perform high-density ion injection twice, so that the complexity of the entire process begins to become a problem.